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16-channel, 16-/14-bit, serial input, voltage-output dac ad5360/ad5361 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2008 analog devices, inc. all rights reserved. features 16-channel dac in 52-lead lqfp and 56-lead lfcsp packages guaranteed monotonic to 16/14 bits nominal output voltage range of ?10 v to +10 v multiple output spans available temperature monitoring function channel monitoring multiplexer gpio function system calibration function allowing user-programmable offset and gain channel grouping and addressing features data error checking feature spi-compatible serial interface 2.5 v to 5.5 v digital interface digital reset ( reset ) clear function to user-defined siggndx simultaneous update of dac outputs applications instrumentation industrial control systems level setting in automatic test equipment (ate) variable optical attenuators (voa) optical line cards functional block diagram n serial interface 8 6 n n 8 8 14 n n n n 8 8 14 14 n n n n n n n n sdi sclk sdo sync busy reset clr state machine control register gpio register gpio mon_out mon_in1 mon_in0 pec temp_out bin/2scomp temp sensor ad5360/ ad5361 a/b select register n = 16 for ad5360 n = 14 for ad5361 a/b select register x1 register m register c register to mux 2s to mux 2s a/b mux mux 2 dac 7 register dac 0 register ofs1 register dac 0 register ofs0 register dac 7 register x2a register x2b register offset dac 0 dac 0 dac 7 offset dac 1 dac 0 dac 7 buffer buffer buffer group 0 group 1 output buffer and power- down control output buffer and power- down control output buffer and power- down control output buffer and power- down control vref0 vout0 vout1 vout2 vout3 vout4 vout5 vout6 vout8 vout9 vout10 vout11 vout12 vout13 vout14 vout15 vout7 siggnd0 siggnd1 vref1 n n n n n n n x1 register m register c register a/b mux mux 2 x2a register x2b register dv cc v dd v ss agnd dgnd ldac n n n n n n n n x1 register m register c register a/b mux mux 2 x2a register x2b register n n n n 2 n n n n x1 register m register c register a/b mux mux 2 x2a register x2b register mux vout0 to vout15 05761-007 figure 1.
ad5360/ad5361 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications ..................................................................................... 4 ac characteristics ........................................................................ 5 timing characteristics ................................................................ 6 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 terminology .................................................................................... 14 functional description .................................................................. 15 dac architecture ....................................................................... 15 channel groups .......................................................................... 15 a /b registers gain/offset adjustment ................................... 16 offset dacs ................................................................................ 16 output amplifier ........................................................................ 17 transfer function ....................................................................... 17 reference selection .................................................................... 17 calibration ................................................................................... 18 reset function ............................................................................ 19 clear function ............................................................................ 19 busy and ldac functions...................................................... 19 bin /2scomp pin ..................................................................... 19 temperature sensor ................................................................... 19 monitor function ....................................................................... 20 gpio pin ..................................................................................... 20 power-down mode .................................................................... 20 thermal monitoring function ................................................. 20 toggle mode ................................................................................ 20 serial interface ................................................................................ 21 spi write mode .......................................................................... 21 spi readback mode ................................................................... 22 register update rates ................................................................ 22 packet error checking ............................................................... 22 channel addressing and special modes ................................. 23 special function mode .............................................................. 24 power supply decoupling ......................................................... 25 power supply sequencing ......................................................... 25 interfacing examples ...................................................................... 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 2/08rev. 0 to rev. a added lfcsp package ....................................................... universal change to dc crosstalk parameter ............................................... 4 change to power dissipation unloaded (p) parameter .............. 5 added t 23 parameter ......................................................................... 6 change to figure 4 ........................................................................... 7 change to table 5 summary ........................................................... 9 added figure 8 ................................................................................ 10 changes to table 6 .......................................................................... 10 changes to calibration section .................................................... 18 changes to reset function section .............................................. 19 added packet error checking section ........................................ 22 updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 27 10/07revision 0: initial version
ad5360/ad5361 rev. a | page 3 of 28 general description the ad5360/ad5361 contain sixteen, 16-/14-bit dacs in a single 52-lead lqfp or 56-lead lfcsp package. they provide buffered voltage outputs with a span four times the reference voltage. the gain and offset of each dac can be independently trimmed to remove errors. for even greater flexibility, the device is divided into two groups of eight dacs, and the output range of each group can be independently adjusted by an offset dac. the ad5360/ad5361 offer guaranteed operation over a wide supply range with v ss from ?4.5 v to ?16.5 v and v dd from +8 v to +16.5 v. the output amplifier headroom requirement is 1.4 v. the ad5360/ad5361 have a high speed 4-wire serial interface, which is compatible with spi, qspi?, microwire?, and dsp interface standards and can handle clock speeds of up to 50 mhz. all the outputs can be updated simultaneously by taking the ldac input low. each channel has a programmable gain register and an offset adjust register. each dac output is amplified and buffered on-chip with respect to an external siggndx input. the dac outputs can also be switched to siggndx via the clr pin.
ad5360/ad5361 rev. a | page 4 of 28 specifications dv cc = 2.5 v to 5.5 v; v dd = 9 v to 16.5 v; v ss = ?16.5 v to ?4.5 v; v ref = 5 v; agnd = dgnd = siggnd = 0 v; r l = open circuit; gain (m), offset (c), and dac offset registers at default value; all specifications t min to t max , unless otherwise noted. table 1. parameter b version 1 unit test conditions/comments accuracy resolution ad5360 16 bits ad5361 14 bits relative accuracy ad5360 4 lsb max ad5361 1 lsb max differential nonlinearity 1 lsb max guaranteed monotonic by design over temperature zero-scale error 15 mv max before calibration full-scale error 20 mv max before calibration gain error 0.1 % fsr before calibration zero-scale error 2 1 lsb typ after calibration full-scale error 2 1 lsb typ after calibration span error of offset dac 75 mv max see the offset dacs section for details voutx 3 temperature coefficient 5 ppm fsr/c typ includes linearity, offset, and gain drift dc crosstalk 4 180 v max typically 20 v; measured channel at midscale, full-scale change on any other channel reference inputs (vref0, vref1) 2 vref input current 10 a max per input; typically 30 na vref range 2 2/5 v min/max 2% for specified operation siggnd input (siggnd0 to siggnd1) 4 dc input impedance 50 k min typically 55 k input range 0.5 v max siggnd gain 0.995/1.005 min/max output characteristics 2 output voltage range v ss + 1.4 v min i load = 1 ma v dd ? 1.4 v max i load = 1 ma nominal output voltage range ?10 to +10 v nominal short-circuit current 15 ma max voutx 3 to dv cc , v dd , or v ss load current 1 ma max capacitive load 2200 pf max dc output impedance 0.5 max monitor pin (mon_out) 4 output impedance dac output at positive full-scale 1000 typ dac output at negative full-scale 500 typ three-state leakage current 100 na typ continuous current limit 2 ma max digital inputs jedec compliant input high voltage 1.7 v min dv cc = 2.5 v to 3.6 v 2.0 v min dv cc = 3.6 v to 5.5 v input low voltage 0.8 v max dv cc = 2.5 v to 5.5 v input current 1 a max reset , sync , sdi, and sclk pins 20 a max clr , bin /2scomp, and gpio pins input capacitance 4 10 pf max
ad5360/ad5361 rev. a | page 5 of 28 parameter b version 1 unit test conditions/comments digital outputs (sdo, busy , gpio, pec ) output low voltage 0.5 v max sinking 200 a output high voltage (sdo) dv cc ? 0.5 v min sourcing 200 a high impedance leakage current 5 a max sdo only high impedance output capacitance 4 10 pf typ temperature sensor (temp_out) 4 accuracy 1 c typ @ 25c 5 c typ ?40c < t < +85c output voltage at 25c 1.46 v typ output voltage scale factor 4.4 mv/c typ output load current 200 a max current source only power-on time 10 ms typ to within 5c power requirements dv cc 2.5/5.5 v min/max v dd 8/16.5 v min/max v ss ?4.5/?16.5 v min/max power supply sensitivity 4 ? full scale/? v dd ?75 db typ ? full scale/? v ss ?75 db typ ? full scale/? dv cc ?90 db typ di cc 2 ma max v cc = 5.5 v, v ih = dv cc , v il = gnd i dd 10 ma max outputs unloaded i ss 10 ma max outputs unloaded power-down mode bit 0 in the control register is 1 di cc 5 a typ i dd 35 a typ i ss ?35 a typ power dissipation power dissipation unloaded (p) 245 mw max v ss = ?12 v, v dd = +12 v, dv cc = 2.5 v junction temperature 130 c max t j = t a + p total ja 1 temperature range for b version: ?40c to +85c. typical specifications are at 25c. 2 specifications are guaranteed for a 5 v reference only. 3 voutx refers to any of vout0 to vout15. 4 guaranteed by design and characterization, not production tested. ac characteristics dv cc = 2.5 v; v dd = 15 v; v ss = ?15 v; v ref = 5 v; agnd = dgnd = siggnd = 0 v; c l = 200 pf; r l = 10 k; gain (m), offset (c), and dac offset registers at default value; all specifications t min to t max , unless otherwise noted. table 2. parameter b version 1 unit test conditions/comments dynamic performance 1 output voltage settling time 20 s typ full-scale change 30 s max dac latch contents alternately loaded with all 0s and all 1s slew rate 1 v/s typ digital-to-analog glitch energy 5 nv-s typ glitch impulse peak amplitude 10 mv max channel-to-channel isolation 100 db typ vref0, vref1 = 2 v p-p, 1 khz dac-to-dac crosstalk 10 nv-s typ digital crosstalk 0.2 nv-s typ digital feedthrough 0.02 nv-s typ effect of input bus activity on dac output under test output noise spectral density @ 10 khz 250 nv/hz typ vref0 = vref1 = 0 v 1 guaranteed by design and characterization, not production tested.
ad5360/ad5361 rev. a | page 6 of 28 timing characteristics dv cc = 2.5 v to 5.5 v; v dd = 9 v to 16.5 v; v ss = ?8 v to ?16.5 v; v ref = 5 v; agnd = dgnd = siggnd = 0 v; c l = 200 pf to gnd; r l = open circuit; gain (m), offset (c), and dac offset registers at default values; all specifications t min to t max , unless otherwise noted. table 3. spi interface (see figure 4 and figure 5 ) parameter 1 , 2 limit at t min , t max unit description t 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 11 ns min sync falling edge to sclk falling edge setup time t 5 20 ns min minimum sync high time t 6 10 ns min 24th sclk falling edge to sync rising edge t 7 5 ns min data setup time t 8 5 ns min data hold time t 9 3 42 ns max sync rising edge to busy falling edge t 10 1/1.5 s typ/max busy pulse width low (single-channel update); see table 8 t 11 600 ns max single-channel update cycle time t 12 20 ns min sync rising edge to ldac falling edge t 13 10 ns min ldac pulse width low t 14 3 s max busy rising edge to dac output response time t 15 0 ns min busy rising edge to ldac falling edge t 16 3 s max ldac falling edge to dac output response time t 17 20/30 s typ/max dac output settling time t 18 140 ns max clr / reset pulse activation time t 19 30 ns min reset pulse width low t 20 400 s max reset time indicated by busy low t 21 270 ns min minimum sync high time in readback mode t 22 4 25 ns max sclk rising edge to sdo valid t 23 80 ns max reset rising edge to busy falling edge 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t f = 2 ns (10% to 90% of dv cc ) and timed from a voltage level of 1.2 v. 3 this is measured with the lo ad circuit shown in figure 2 . 4 this is measured with the lo ad circuit shown in figure 3 . to output pin c l 50pf r l 2.2k ? v ol dv cc 05761-008 v oh (min) ? v ol (max) 2 200a i ol 200a i oh t o output pin c l 50pf 0 5761-009 figure 2. load circuit for busy timing diagram figure 3. load circuit for sdo timing diagram
ad5360/ad5361 rev. a | page 7 of 28 sclk sync sdi busy v outx 1 v outx 2 voutx reset voutx clr 1 2 24 t 8 t 12 t 10 t 13 t 17 t 14 t 15 t 13 t 17 t 9 t 7 t 5 t 4 t 2 t 6 db23 db0 t 16 1 ldac active during busy. 2 ldac active after busy. busy ldac 1 ldac 2 1 t 3 t 20 t 23 t 18 t 18 t 19 24 t 11 t 1 05761-010 figure 4. spi write timing
ad5360/ad5361 rev. a | page 8 of 28 sdi sdo 48 nop condition selected register data clocked out t 22 t 21 lsb from previous write sclk sync db0 db0 db0 db0 db23 db23 db23 db15 05761-011 input word specifies register to be read figure 5. spi read timing dac code full-scale error + zero-scale error zero-scale error vmin 0 2 n ? 1 vmax ideal transfer function n = 16 for ad5360 n = 14 for ad5361 actual transfer function output voltage 05761-001 figure 6. dac tr ansfer function
ad5360/ad5361 rev. a | page 9 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. transient currents of up to 60 ma do not cause scr latch-up. table 4. parameter rating v dd to agnd ?0.3 v to +17 v v ss to agnd ?17 v to +0.3 v dv cc to dgnd ?0.3 v to +7 v digital inputs to dgnd ?0.3 v to dv cc + 0.3 v digital outputs to dgnd ?0.3 v to dv cc + 0.3 v vref0, vref1 to agnd ?0.3 v to +5.5 v vout0 to vout15 to agnd v ss ? 0.3 v to v dd + 0.3 v siggnd0, siggnd1 to agnd ?1 v to +1 v agnd to dgnd ?0.3 v to +0.3 v mon_in0, mon_in1, mon_out to agnd v ss ? 0.3 v to v dd + 0.3 v operating temperature (t a ) industrial (b version) ?40c to +85c storage ?65c to +150c junction (t j max) 130c ja thermal impedance 52-lead lqfp 38c/w 56-lead lfcsp 25c/w reflow soldering peak temperature 230c time at peak temperature 10 sec to 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5360/ad5361 rev. a | page 10 of 28 pin configuration and fu nction descriptions 05761-022 52 51 50 49 48 43 42 41 40 47 46 45 44 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 13 12 39 38 37 36 35 34 33 32 31 30 29 28 27 nc vout8 vout9 vout10 vout11 siggnd1 vout12 vout13 vout14 vout15 nc nc nc ldac clr reset bin/2scomp busy gpio mon_out mon_in0 nc nc v dd v ss vref1 vout4 siggnd0 vout3 vout2 vout1 vout0 temp_out mon_in1 vref0 nc v ss v dd nc nc = no connect agnd dv cc sdo pec sdi sclk sync dv cc dgnd vout 7 vout 6 vout 5 dgnd ad5360/ ad5361 pin 1 indicator top view (not to scale) pin 1 indicator nc = no connect 1 reset 2 bin/2scomp 3 busy 4 gpio 5 mon_out 6 mon_in0 7 nc 8 nc 9 nc 10 nc 11 nc 12 v dd 13 v ss 14 vref1 35 temp_ou t 36 vout0 37 vout1 38 vout2 39 vout3 40 siggnd0 41 vout4 42 vout5 34 mon_in1 33 vref0 32 nc 31 nc 30 v ss 29 v dd 15 nc 16 nc 17 vout8 19 vout10 21 siggnd1 20 vou t11 22 vout12 23 v out13 24 vout14 25 vout15 26 nc 27 nc 28 nc 18 vout9 45 dgnd 46 dv cc 47 sync 48 sclk 49 sdi 50 pec 51 sdo 52 dv cc 53 d gnd 54 agnd 44 v out7 43 vout6 top view (not to scale) ad5360/ ad5361 55 ldac 56 clr 0 5761-028 figure 7. 52-lead lqfp pin configuration figure 8. 56-lead lfcsp pin configuration table 5. lqfp pin function descriptions pin no. mnemonic description lqfp lfcsp 1 55 ldac load dac logic input (active low). see the busy and ldac functions section for more information. 2 56 clr asynchronous clear input (level sensitive, active low). see the clear function section for more information. 3 1 reset digital reset input. 4 2 bin /2scomp data format digital input. connecting this pin to dgnd selects offset binary. connecting this pin to logic 1 selects twos complement. this input has a weak pull-down. 5 3 busy digital input/open-drain output. busy is open drain when it is an output. see the busy and ldac functions section for more information. 6 4 gpio digital i/o pin. this pin can be configur ed as an input or output that can be read or programmed high or low via the serial interface. when configured as an input, it has a weak pull-down. 7 5 mon_out analog multiplexer output. any dac output, the mon_in0 input, or the mon_in1 input can be swit ched to this output. 8, 32 6, 34 mon_in0, mon_in1 analog multiplexer inputs. can be switched to mon_out. 9, 10, 14, 24, 25, 26, 27, 30 7 to 11, 15, 16, 26 to 28, 31, 32 nc no connect. 11, 28 12, 29 v dd positive analog power supply; +9 v to +16.5 v for specified performance. these pins should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 12, 29 13, 30 v ss negative analog power supply; ?16.5 v to ?8 v for specified performance. these pins should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 13 14 vref1 reference input for dac 8 to dac 15. this voltage is referred to agnd. 19 21 siggnd1 reference ground for dac 8 to dac 15. vout8 to vout15 are referenced to this voltage. 31 33 vref0 reference input for dac 0 to dac 7. this voltage is referred to agnd. 33 35 temp_out provides an output voltage proportional to chip temperature. this is typically 1.46 v at 25c with an output variation of 4.4 mv/c. 34 to 37, 39 to 42, 15 to 18, 20 to 23 36 to 39, 41 to 44, 17 to 20, 22 to 25 vout0 to vout15 dac outputs. buffered analog outputs for each of the 16 dac channels. each analog output is capable of driving an output load of 10 k to ground. typical output impedance of these amplifiers is 0.5 .
ad5360/ad5361 rev. a | page 11 of 28 pin no. mnemonic description lqfp lfcsp 38 40 siggnd0 reference ground for dac 0 to dac 7. vout0 to vout7 are referenced to this voltage. 43, 51 45, 53 dgnd ground for all digital circuitry. both dgnd pins should be connected to the dgnd plane. 44, 50 46, 52 dv cc logic power supply; 2.5 v to 5.5 v. these pins should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 45 47 sync active low or sync input for spi interface. this is the frame synchronization signal for the spi serial interface. see , , and the section for more details. figure 4 figure 5 serial interface 46 48 sclk serial clock input for spi interface. see figure 4 , figure 5 , and the serial interface section for more details. 47 49 sdi serial data input for spi interface. see figure 4 , figure 5 , and the serial interface section for more details. 48 50 pec packet error check output. this is an open-drain output with a 50 k pull-up that goes low if the packet error check fails. 49 51 sdo serial data output for spi interface. see figure 4 , figure 5 , and the serial interface section for more details. 52 54 agnd ground for all analog circuitry. the agnd pin should be connected to the agnd plane. ep connect to v ss exposed paddle.
ad5360/ad5361 rev. a | page 12 of 28 typical performance characteristics 2 ?2 0 65535 dac code inl (lsb) 1 0 ?1 16384 32768 49152 05761-012 0.0050 ?0.0050 05 time (s) amplitude (v) 0 0.0025 ?0.0025 1234 t a = 25c v ss = ?15v v dd = +15v v ref = +4.096v 05761-015 figure 9. typical ad5360 inl plot figure 12. digital crosstalk 1.0 ?1.0 08 temperature (c) inl error (lsb) 0 1.0 ?1.0 0 65535 dac code dnl (lsb) 0 0.5 ?0.5 16384 32768 49152 05761-016 0.5 0 ?0.5 20 40 60 v dd = +15v v ss = ?15v dv cc = +5v v ref = +3v 05761-013 figure 10. typical inl error vs. temperature figure 13. typical ad5360 dnl plot 600 0 05 frequency (hz) output noise (nv/ hz) 200 300 400 500 100 123 4 05761-017 ?0.02 ?0.01 0 amplitude (v) 024681 time (s) 0 t a = 25c v ss = ?15v v dd = +15v v ref = +4.096v 0 5761-014 figure 11. analog crosstalk due to ldac figure 14. noise spectral density
ad5360/ad5361 rev. a | page 13 of 28 0.50 0.45 0.40 0.35 0.30 0.25 ?40 80 temperature (c) i cc (ma) ?20 0 20 60 40 dv cc = +5.5v dv cc = +3.6v dv cc = +2.5v v ss = ?12v v dd = +12v v ref = +3v 05761-018 figure 15. i cc vs. temperature 8.0 7.5 7.0 6.5 6.0 ?40 80 temperature (c) i dd /i ss (ma) ?20 0 20 60 40 v ss = ?12v v dd = +12v v ref = +3v i ss i dd 05761-019 figure 16. i dd /i ss vs. temperature 14 12 10 8 6 4 2 0 7.00 7.25 7.50 7.75 8.00 v dd = 15v v ss = 15v t a = 25c number of units i dd (ma) 0 5761-020 figure 17. typical i dd distribution dv cc = 5v t a = 25c 05761-021 6 0 0.48 0.58 i cc (ma) number of units 5 4 3 2 1 0.50 0.52 0.54 0.56 figure 18. typical i cc distribution 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 ?40 ?25 ?10 5 20 35 50 65 80 05761-027 voltage (v) temperature (c) figure 19. temp_out voltage vs. temperature mon_out current (ma) voutx ? mon_out (v) 05761-026 1.0 ?1.0 ?1.0 1.0 0 0.5 ?0.5 ?0.5 0 0.5 full-scale zero-scale midscale figure 20. (voutx ? mon_out voltage) vs. mon_out current
ad5360/ad5361 rev. a | page 14 of 28 terminology integral nonlinearity (inl) integral nonlinearity, or relative accuracy, is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (lsb). differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. zero-scale error zero-scale error is the error in the dac output voltage when all 0s are loaded into the dac register. zero-scale error is a measure of the difference between vout (actual) and vout (ideal), expressed in millivolts, when the channel is at its minimum value. zero-scale error is mainly due to offsets in the output amplifier. full-scale error full-scale error is the error in dac output voltage when all 1s are loaded into the dac register. full-scale error is a measure of the difference between vout (actual) and vout (ideal), expressed in millivolts, when the channel is at its maximum value. it does not include zero- scale error. gain error gain error is the difference between full-scale error and zero- scale error. it is expressed in millivolts. gain error = full-scale error ? zero-scale error vout temperature coefficient this includes output error contributions from linearity, offset, and gain drift. dc output impedance dc output impedance is the effective output source resistance. it is dominated by package lead resistance. dc crosstalk the dac outputs are buffered by op amps that share common v dd and v ss power supplies. if the dc load current changes in one channel (due to an update), this can result in a further dc change in one or more channel outputs. this effect is more significant at high load currents and reduces as the load currents are reduced. with high impedance loads, the effect is virtually immeasurable. multiple v dd and v ss terminals are provided to minimize dc crosstalk. output voltage settling time the amount of time it takes for the output of a dac to settle to a specified level for a full-scale input change. digital-to-analog glitch energy this is the amount of energy injected into the analog output at the major code transition. it is specified as the area of the glitch in nv-s. it is measured by toggling the dac register data between 0x7fff and 0x8000 (ad5360) or 0x1fff and 0x 2000 (ad5361). channel-to-channel isolation channel-to-channel isolation refers to the proportion of input signal from the reference input of one dac that appears at the output of another dac operating from another reference. it is expressed in decibels and measured at midscale. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog output change at another converter. it is specified in nv-s. digital crosstalk digital crosstalk is defined as the glitch impulse transferred to the output of one converter due to a change in the dac register code of another converter and is specified in nv-s. digital feedthrough when the device is not selected, high frequency logic activity on the devices digital inputs can be capacitively coupled both across and through the device to show up as noise on the voutx pins. it can also be coupled along the supply and ground lines. this noise is digital feedthrough. output noise spectral density output noise spectral density is a measure of internally generated random noise. random noise is characterized as a spectral density (voltage per hz). it is measured by loading all dacs to midscale and measuring noise at the output. it is measured in nv/hz.
ad5360/ad5361 rev. a | page 15 of 28 functional description dac architecture the ad5360/ad5361 contain 16 dac channels and 16 output amplifiers in a single package. the architecture of a single dac channel consists of a 16-bit resistor-string dac in the case of the ad5360 and a 14-bit dac in the case of the ad5361, followed by an output buffer amplifier. the resistor-string section is simply a string of resistors, of equal value, from vref0 or vref1 to agnd. this type of architecture guarantees dac monotonicity. the 16-/14-bit binary digital code loaded to the dac register determines at which node on the string the voltage is tapped off before being fed into the output amplifier. the output amplifier multiplies the dac output voltage by 4. the nominal output span is 12 v with a 3 v reference and 20 v with a 5 v reference. channel groups the 16 dac channels of the ad5360/ad5361 are arranged into two groups of eight channels. the eight dacs of group 0 derive their reference voltage from vref0. group 1 derives its refer- ence voltage from vref1. each group has its own signal ground pin. table 6. ad5360/ad5361 registers register name word length in bits description x1a (group) (channel) 16 (14) input data register a, one for each dac channel. x1b (group) (channel) 16 (14) input data register b, one for each dac channel. m (group) (channel) 16 (14) gain trim register, one for each dac channel. c (group) (channel) 16 (14) offset trim register, one for each dac channel. x2a (group) (channel) 16 (14) output data register a, one for each dac channel. these registers store the final, calibrated dac data after gain and offset trimming. they are not readable or directly writable. x2b (group) (channel) 16 (14) output data register b, one for each dac channel. these registers store the final, calibrated dac data after gain and offset trimming. they are not readable or directly writable. dac (group) (channel) data registers from which the dacs take their final input data. the dac registers are updated from the x2a or x2b registers. they are not readable or directly writable. ofs0 14 offset dac 0 data register, sets offset for group 0. ofs1 14 offset dac 1 data register, sets offset for group 1. control 5 control register. monitor 6 monitor enable and configuration register. gpio 2 gpio configuration register. table 7. ad5360/ad5361 input register default values register name ad5360 default value ad5361 default value x1a, x1b 0x8000 0x2000 m 0xffff 0x3fff c 0x8000 0x2000 ofs0, ofs1 0x2000 0x2000 control 0x00 0x00 a /b select 0 and a /b select 1 0x00 0x00
ad5360/ad5361 rev. a | page 16 of 28 a /b registers gain/offset adjustment each dac channel has seven data registers. the actual dac data word can be written to either the x1a or x1b input register, depending on the setting of the a /b bit in the control register. if the a /b bit is 0, data is written to the x1a register. if the a /b bit is 1, data is written to the x1b register. note that this single bit is a global control and affects every dac channel in the device. it is not possible to set up the device on a per- channel basis so that some writes are to the x1a register and some writes are to the x1b register. mux dac dac register mux x1a register x1b register m register c register x2a register x2b register 05761-023 figure 21. data registers associated with each dac channel each dac channel also has a gain register (m) and an offset (c) register, which allow trimming out of the gain and offset errors of the entire signal chain. data from the x1a register is oper- ated on by a digital multiplier and adder by the contents of the m and c registers. the calibrated dac data is then stored in the x2a register. similarly, data from the x1b register is operated on by the multiplier and adder and stored in the x2b register. although a multiplier and adder symbol are shown for each channel, there is only one multiplier and one adder in the device, which are shared among all channels. this has implications for the update speed when several channels are updated at once, as described in the register update rates section. each time data is written to the x1a register, or to the m or c register with the a /b control bit set to 0, the x2a data is recalculated and the x2a register is automatically updated. similarly, x2b is updated each time data is written to x1b, or to m or c with a /b set to 1. the x2a and x2b registers are not readable or directly writable by the user. data output from the x2a and x2b registers is routed to the final dac register by a multiplexer. an 8-bit a /b select register associated with each group of eight dacs controls whether each individual dac takes its data from the x2a or x2b register. if a bit in this register is 0, the dac takes its data from the x2a register; if 1, the dac takes its data from the x2b register (bit 0 through bit 7 control dac 0 through dac 7, respectively). note that because there are 16 bits in two registers, it is possible to set up, on a per-channel basis, whether each dac takes its data from the x2a register or x2b register. a global command is also provided that sets all bits in the a /b select registers to 0 or to 1. all dacs in the ad5360/ad5361 can be updated simultane- ously by taking ldac low, when each dac register is updated from either its x2a or x2b register, depending on the setting of the a /b select registers. the dac register is not readable or directly writable by the user. offset dacs in addition to the gain and offs et trim for each dac, there are two 14-bit offset dacs, one for group 0, and one for group 1. these allow the output range of all dacs connected to them to be offset within a defined range. thus, subject to the limitations of headroom, it is possible to set the output range of group 0 and/or group 1 to be unipolar positive, unipolar negative, or bipolar (either symmetrical or asymmetrical) about 0 v. the dacs in the ad5360/ad5361 are factory trimmed with the offset dacs set at their default values. this gives the best offset and gain performance for the default output range and span. when the output range is adjusted by changing the value of the offset dac, an extra offset is introduced due to the gain error of the offset dac. the amount of offset is dependent on the magnitude of the reference and how much the offset dac moves from its default value. this offset is shown in table 1 . the worst-case offset occurs when th e offset dac is at positive full scale or negative full scale. this value can be added to the offset present in the main dac of a chan nel to give an indication of the overall offset for that channel. in most cases, the offset can be removed by programming the c register of the channel with an appropriate value. the extra offset caused by the offset dacs needs to be taken into account only when the offset dac is changed from its default value. figure 22 shows the allowable code range that can be loaded to the offset dac, and this is dependent on the reference value used. thus, for a 5 v reference, the offset dac should not be programmed with a value greater than 8192 (0x2000). 0 4096 8192 12288 16383 offset dac code 0 1 2 3 4 v r e f ( v ) 5 reserved 0 5761-005 figure 22. offset dac code range
ad5360/ad5361 rev. a | page 17 of 28 output amplifier because the output amplifiers can swing to 1.4 v below the positive supply and 1.4 v above the negative supply, this limits how much the output can be offset for a given reference voltage. for example, it is not possible to have a unipolar output range of 20 v because the maximum supply voltage is 16.5 v. clr clr clr dac channel offset dac output r6 10k ? r2 20k ? s3 s2 s1 r4 60k ? r3 20k ? s iggnd siggnd r5 60k ? r1 20k ? 05761-006 figure 23. output ampl ifier and offset dac figure 23 shows details of a dac output amplifier and its connections to the offset dac. on power-up, s1 is open, disconnecting the amplifier from the output. s3 is closed, so the output is pulled to siggnd. s2 is also closed to prevent the output amplifier from being open-loop. if clr is low at power-up, the output remains in this condition until clr is taken high. the dac registers can be programmed, and the outputs assume the programmed values when clr is taken high. even if clr is high at power-up, the output remains in this condition until v dd > 6 v and v ss < ?4 v and the initialization sequence has finished. the outputs then go to their power-on default values. transfer function the output voltage of a dac in the ad5360/ad5361 is dependent on the value in the input register, the value of the m and c registers, and the value in the offset dac. the transfer functions for the ad5360/ad5361 are shown in the following sections. ad5360 transfer function the input code is the value in the x1a or x1b register that is applied to dac (x1a, x1b default code = 32,768) dac_code = input_code (m + 1)/2 16 + c ? 2 15 dac output voltage v out = 4 v ref ( dac_code ? ( offset_code 4))/ 2 16 + v siggnd where: dac_code should be within the range of 0 to 65,535. v ref = 3.0 v, for a 12 v span. v ref = 5.0 v, for a 20 v span. m = code in gain register ? default code = 2 16 C 1. c = code in offset register ? default code = 2 15 . offset_code is the code loaded to the offset dac. it is multiplied by 4 in the transfer function because this dac is a 14-bit device. on power-up, the default code loaded to the offset dac is 8192 (0x2000). with a 10 v reference, this gives a span of ?10 v to +10 v. ad5361 transfer function the input code is the value in the x1a or x1b register that is applied to dac (x1a, x1b default code = 8192) dac_code = input_code ( m + 1)/2 14 + c ? 2 13 dac output voltage v out = 4 v ref ( dac_code ? offset_code )/2 14 + v siggnd where: dac_code should be within the range of 0 to 16,383. v ref = 3.0 v, for a 12 v span. v ref = 5.0 v, for a 20 v span. m = code in gain register ? default code = 2 14 ? 1. c = code in offset register ? default code = 2 13 . offset_code is the code loaded to the offset dac. on power-up, the default code loaded to the offset dac is 8192 (0x2000). with a 5 v reference, this gives a span of ?10 v to +10 v. reference selection the ad5360/ad5361 have two reference input pins. the voltage applied to the reference pins determines the output voltage span on vout0 to vout15. vref0 determines the voltage span for vout0 to vout7 (group 0), and vref1 determines the voltage span for vout8 to vout15 (group 1). the reference voltage applied to each vref pin can be different, if required, allowing each group of eight channels to have a different voltage span. the output voltage range and span can be adjusted by programming the offset register and gain register for each channel as well as programming the offset dac. if the offset and gain features are not used (that is, the m and c registers are left at their default values), the required reference levels can be calculated as follows: vref = ( vout max ? vout min )/4 if the offset and gain features of the ad5360/ad5361 are used, the required output range is slightly different. the chosen output range should take into account the system offset and gain errors that need to be trimmed out. therefore, the chosen output range should be larger than the actual, required range. th e required reference levels can be calculated as follows: 1. identify the nominal output range on vout. 2. identify the maximum offset span and the maximum gain required on the full output signal range. 3. calculate the new maximum output range on vout, including the expected maximum offset and gain errors.
ad5360/ad5361 rev. a | page 18 of 28 4. choose the new required vout max and vout min , keeping the vout limits centered on the nominal values. note that v dd and v ss must provide sufficient headroom. 5. calculate the value of vref as follows: vref = (vout max ? vout min )/ 4 reference selection example nominal output range = 20 v (?10 v to +10 v) offset error = 100 mv gain error = 3% siggnd = agnd = 0 v gain error = 3% maximum positive gain error = +3% output range including gain error = 20 + 0.03 (20) = 20.6 v offset error = 100 mv maximum offset error span = 2 (100 mv) = 0.2 v output range including gain error and offset error = 20.6 v + 0.2 v = 20.8 v vref calculation actual output range = 20.6 v, that is, ?10.3 v to +10.3 v (centered); vref = (10.3 v + 10.3 v)/4 = 5.15 v i f the solution yields an inconvenient reference level, the user can adopt one of the following approaches: ? use a resistor divider to divide down a convenient, higher reference level to the required level. ? select a convenient reference level above vref and modify the gain and offset register s to digitally downsize the reference. in this way, the user can use almost any conven- ient reference level but may reduce the performance by overcompaction of the transfer function. ? use a combination of these two approaches. calibration the user can perform a system calibration on the ad5360 and ad5361 to reduce gain and offset errors to below 1 lsb. this is achieved by calculating new values for the m and c registers and reprogramming them. reducing zero-scale and full-scale error ze ro-scale error can be reduced as follows: 1. set the output to the lowest possible value. 2. measure the actual output voltage and compare it with the required value. this gives the zero-scale error. 3. calculate the number of lsbs equivalent to the error and add this from the default value of the c register. note that only negative zero-scale error can be reduced. fu ll-scale error can be reduced as follows: 1. measure the zero-scale error. 2. set the output to the highest possible value. 3. measure the actual output voltage and compare it with the required value. add this error to the zero-scale error. this is the span error, which includes full-scale error. 4. calculate the number of lsbs equivalent to the span error and subtract it from the default value of the m register. note that only positive full-scale error can be reduced. the m and c registers should not be programmed until both zero-scale errors and full-scale errors have been calculated. ad5360 calibration example this example assumes that a ?10 v to +10 v output is required. the dac output is set to ?10 v but is measured at ?10.03 v. this gives a zero-scale error of ?30 mv. 1 lsb = 20 v/65,536 = 305.176 v 30 mv = 98 lsbs the full-scale error can now be removed. the output is set to +10 v, and a value of +10.02 v is measured. the full-scale error is +20 mv. the span error is +20 mv ? (?30 mv) = +50 mv. +50 mv = 164 lsbs th e errors can now be removed. 1. 98 lsbs should be added to the default c register value; (32,768 + 98) = 32,866. 2. 32,866 should be programmed to the c register. 3. 164 lsbs should be subtracted from the default m register value; (65,535 ? 164) = 65,371. 4. 65,371 should be programmed to the m register. additional calibration the techniques described in the previous section are usually enough to reduce the zero-scale errors and full-scale errors in most applications. however, there are limitations whereby the errors may not be sufficiently removed. for example, the offset (c) register can only be used to reduce the offset caused by the negative zero-scale error. a positive offset cannot be reduced. likewise, if the maximum voltage is below the ideal value, that is, a negative full-scale error, the gain (m) register cannot be used to increase the gain to compensate for the error. these limitations can be overcome by increasing the refer- ence value. with a 2.5 v reference, a 10 v span is achieved. the ideal voltage range, for the ad5360 or ad5361, is ?5 v to +5 v. using a 2.6 v reference increases the range to ?5.2 v to +5.2 v. clearly, in this case, the offset and gain errors are insignificant and the m and c registers can be used to raise the negative voltage to ?5 v and then reduce the maximum voltage down to +5 v to give the most accurate values possible.
ad5360/ad5361 rev. a | page 19 of 28 reset function the reset function is initiated by the reset pin. on the rising edge of reset , the ad5360/ad5361 state machine initiates a reset sequence to reset the x, m, and c registers to their default values. this sequence typically takes 300 s, and the user should not write to the part during this time. on power-up, it is recom- mended that the user bring reset high as soon as possible to properly initialize the registers. when the reset sequence is complete (and provided that clr is high), the dac output is at a potential specified by the default register settings, which are equivalent to siggndx. the dac outputs remain at siggndx until the x, m, or c register is updated and ldac is taken low. the ad5360/ad5361 can be returned to the default state by pulsing reset low for at least 30 ns. note that, because the reset function is rising edge trig- gered, bringing reset low has no effect on the operation of the ad5360/ad5361. clear function clr is an active low input that should be high for normal operation. the clr pin has an internal 500 k pull-down resistor. when clr is low, the input to each of the dac output buffer stages (vout0 to vout15) is switched to the externally set potential on the relevant siggndx pin. while clr is low, all ldac pulses are ignored. when clr is taken high again, the dac outputs return to their previous values. the contents of input registers and dac register 0 to dac register 15 are not affected by taking clr low. to prevent glitches appearing on the outputs, clr should be brought low whenever the output span is adjusted by writing to the offset dac. busy and ldac functions the value of an x2 (a or b) register is calculated each time the user writes new data to the corresponding x1, c, or m register. during the calculation of x2, the busy output goes low. while busy is low, the user can continue writing new data to the x1, m, or c register (see the register update rates section for more details), but no dac output updates can take place. the busy pin is bidirectional and has a 50 k internal pull-up resistor. when multiple ad5360 or ad5361 devices may be used in one system, the busy pins can be tied together. this is useful when it is required that no dac in any device be updated until all other dacs are ready. when each device has finished updating the x2 (a or b) register, it releases the busy pin. if another device has not finished updating its x2 registers, it holds busy low, thus delaying the effect of ldac going low. the dac outputs are updated by taking the ldac input low. if ldac goes low while busy is active, the ldac event is stored and the dac outputs update immediately after busy goes high. a user can also hold the ldac input permanently low. in this case, the dac outputs update immediately after busy goes high. whenever the a /b select registers are written to, busy also goes low, for approximately 600 ns. the ad5360/ad5361 have flexible addressing that allows writing of data to a single channel, all channels in a group, the same channel in group 0 and group 1, or all channels in the device. this means that 1, 2, 8, or 16 dac register values may need to be calculated and updated. because there is only one multiplier shared among 16 channels, this task must be done sequentially, so the length of the busy pulse varies according to the number of channels being updated. table 8. busy pulse widths action busy pulse width 1 loading input, c, or m to 1 channel 2 1.5 s maximum loading input, c, or m to 2 channels 2.1 s maximum loading input, c, or m to 8 channels 5.7 s maximum loading input, c, or m to 16 channels 10.5 s maximum 1 busy pulse width = ((number of cha nnels + 1) 600 ns) + 300 ns. 2 a single channel update is typically 1 s. the ad5360/ad5361 contain an extra feature whereby a dac register is not updated unless its x2a or x2b register has been written to since the last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the x2a or x2b registers, depending on the setting of the a /b select register. however, the ad5360/ ad5361 update the dac register only if the x2a or x2b data has changed, thereby removing unnecessary digital crosstalk. bin /2scomp pin the bin /2scomp pin determines if the output data is presented as offset binary or twos complement. if this pin is low, the data is straight binary. if it is high, the data is twos complement. this affects only the x, c, and offset dac registers; the m register and the control and command data are interpreted as straight binary. temperature sensor the on-chip temperature sensor provides a voltage output at the temp_out pin that is linearly proportional to the centigrade temperature scale. the typical accuracy of the temperature sensor is 1c at +25c and 5c over the ?40c to +85c range. its nominal output voltage is 1.46 v at +25c, varying at 4.4 mv/c. its low output impedance, low self- heating, and linear output simplify interfacing to temperature control circuitry and analog-to-digital converters.
ad5360/ad5361 rev. a | page 20 of 28 monitor function the ad5360/ad5361 contain a channel monitor function that consists of an analog multiplexer addressed via the serial interface, allowing any channel output to be routed to this pin for monitoring using an external adc. in addition, two monitor inputs, mon_in0 and mon_in1, are provided, which can also be routed to mon_out. the monitor function is controlled by the monitor register, which allows the monitor output to be enabled or disabled, and selection of a dac channel or one of the monitor pins. when disabled, the monitor output is high impedance, so several monitor outputs can be connected in parallel and only one enabled at a time. table 9 shows the control register settings relevant to the monitor function. table 9. control register monitor functions f5 f4 f3 f2 f1 f0 function 0 x x x x x mon_out disabled 1 x x x x x mon_out enabled 1 0 0 0 0 0 mon_out = vout0 1 0 0 0 0 1 mon_out = vout1 1 0 1 1 1 1 mon_out = vout15 1 1 0 0 0 0 mon_out = mon_in0 1 1 0 0 0 1 mon_out = mon_in1 the multiplexer is implemented as a series of analog switches. because this could conceivably ca use a large amount of current to flow from the input of the multiplexer, that is, voutx or mon_inx to the output of the multiplexer, mon_out, care should taken to ensure that whatever is connected to the mon_out pin is of high enough impedance to prevent the continuous current limit specification from being exceeded. because the mon_out pin is not buffered, the amount of current drawn from this pin creates a voltage drop across the switches, which in turn leads to an error in the voltage being monitored. where accuracy is important, it is recommended that the mon_out pin be buffered. figure 20 shows the typical error due to the mon_out current gpio pin the ad5360/ad5361 have a general-purpose i/o pin, gpio. this can be configured as an input or an output and read back or programmed (when configured as an output) via the serial interface. typical applications for this pin include monitoring the status of a logic signal, monitoring a limit switch, or controlling an external multiplexer. the gpio pin is configured by writing to the gpio register, which has the special function code of 001101 (see table 14 and table 15 ). when bit f1 is set, the gpio pin becomes an output and f0 determines whether the pin is high or low. the gpio pin can be set as an input by writing 0 to both f1 and f0. the status of the gpio pin can be determined by initiating a read operation using the appropriate bits in table 16 . the status of the pin is indicated by the lsb of the register read. power-down mode the ad5360/ad5361 can be powered down by setting bit 0 in the control register to 1. this turns off the dacs, thus reducing the current consumption. the dac outputs are connected to their respective siggnd potentials. the power-down mode does not change the contents of the registers, and the dacs return to their previous voltage when the power-down bit is cleared to 0. thermal monitoring function the ad5360/ad5361 can be programmed to power down the dacs if the temperature on the die exceeds 130c. setting bit 1 in the control register to 1 (see table 15 ) enables this function. if the die temperature exceeds 130c, the ad5360/ad5361 enter a temperature power-down mode, which is equivalent to setting the power-down bit in the control register. to indicate that the ad5360/ad5361 have entered temperature shutdown mode, bit 4 of the control register is set to 1. the ad5360/ad5361 remain in temperature shutdown mode, even if the die tempera- ture falls, until bit 1 in the control register is cleared to 0. toggle mode the ad5360/ad5361 have two x2 registers per channel, x2a and x2b, which can be used to switch the dac output between two levels with ease. this approach greatly reduces the overhead required by a microprocessor, which would otherwise have to write to each channel individually. when the user writes to either the x1a, x2a, m, or c register, the calculation engine takes a certain amount of time to calculate the appropriate x2a or x2b values. if the application only requires that the dac output switch between two levels, such as a data generator, any method that reduces the amount of calculation time encoun- tered is advantageous. for the data generator example, the user should set the high and low levels for each channel once, by writing to the x1a and x1b registers. the values of x2a and x2b are calculated and stored in their respective registers. the calculation delay, therefore, only happens during the setup phase, that is, when programming the initial values. to toggle a dac output between the two levels, it is only required to write to the relevant a /b select register to set the mux 2 register bit. furthermore, because there are eight mux 2 control bits per register, it is possible to update eight channels with a single write. shows the bits that correspond to each dac output. table 17
ad5360/ad5361 rev. a | page 21 of 28 serial interface the ad5360/ad5361 contain a high speed spi operating at clock frequencies up to 50 mhz (20 mhz for read operations). to minimize both the power consumption of the device and on-chip digital noise, the interface powers up fully only when the device is being written to, that is, on the falling edge of sync . the serial interface is 2.5 v lvttl-compatible when operating from a 2.5 v to 3.6 v dv cc supply. it is controlled by four pins: sync (frame synchronization input), sdi (serial data input), sclk (clocking of data in and out of the device), and sdo (serial data output for data readback). spi write mode the ad5360/ad5361 allow writing of data via the serial inter- face to every register directly accessible to the serial interface, which are all registers except the x2a, x2b, and dac registers. the x2a and x2b registers are updated when writing to the x1a, x1b, m, and c registers, and the dac registers are updated by ldac . the serial word (see or ) is 24 bits long; 16 or 14 of these bits are data bits, six bits are address bits, and two bits are mode bits that determine what is done with the data. two bits are reserved on the ad5361. table 10 table 11 the serial interface works with both a continuous and a burst (gated) serial clock. serial data applied to sdi is clocked into the ad5360/ad5361 by clock pulses applied to sclk. the first falling edge of sync starts the write cycle. at least 24 falling clock edges must be applied to sclk to clock in 24 bits of data, before sync is taken high again. if sync is taken high before the 24th falling clock edge, the write operation is aborted. if a continuous clock is used, sync must be taken high before the 25th falling clock edge. this inhibits the clock within the ad5360/ad5361. if more than 24 falling clock edges are applied before sync is taken high again, the input data is corrupted. if an externally gated clock of exactly 24 pulses is used, sync may be taken high any time after the 24th falling clock edge. the input register addressed is updated on the rising edge of sync . for another serial transfer to take place, sync must be taken low again. table 10. ad5360 serial word bit assignation i23 i22 i21 i20 i19 i18 i17 i16 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 m1 m0 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 11. ad5361 serial word bit assignation i23 i22 i21 i20 i19 i18 i17 i16 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 1 i0 1 m1 m0 a5 a4 a3 a2 a1 a0 d13 d12 d11 d1 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 i1 and i0 are reserved for future use and should be 0 when writing the serial word. these bits read back as 0.
ad5360/ad5361 rev. a | page 22 of 28 spi readback mode the ad5360/ad5361 allow data readback via the serial inter- face from every register directly accessible to the serial interface, which is all registers except the x2a, x2b, and dac data registers. to read back a register, it is first necessary to tell the ad5360/ad5361 which register is to be read. this is achieved by writing a word whose first two bits are the special function code 00 to the device. the remaining bits then determine if the operation is a readback and which register is to be read back, or if it is a write to of the special function registers, such as the control register. if a readback command is written to a special function register, data from the selected register is clocked out of the sdo pin during the next spi operation. the sdo pin is normally three- stated but becomes driven as soon as a read command is issued. the pin remains driven until the registers data is clocked out. see figure 5 for the read timing diagram. note that, due to the timing requirements of t 22 (25 ns), the maximum speed of the spi interface during a read operation should not exceed 20 mhz. register update rates the value of the x2a or x2b register is calculated each time the user writes new data to the corresponding x1, c, or m register. the calculation is performed by a three-stage process. the first two stages take approximately 600 ns each, and the third stage takes approximately 300 ns. when the write to a x1, c, or m register is complete, the calculation process begins. if the write operation involves the update of a single dac channel, the user is free to write to another register provided that the write operation does not finish until the first stage calculation is complete, that is, 600 ns after the completion of the first write operation. if a group of channels is being updated by a single write operation, the first stage calculation is repeated for each channel, taking 600 ns per channel. in this case, the user should not complete the next write operation until this time has elapsed. packet error checking to verify that data has been received correctly in noisy environ- ments, the ad5360/ad5361 offer the option of error checking based on an 8-bit (crc-8) cyclic redundancy check. the device controlling the ad5360/ad5361 should generate an 8-bit checksum using the polynomial c(x) = x 8 + x 2 + x 1 +1. the checksum is added to the end of the data word, and 32 data bits are sent to the ad5360/ad5361 before taking sync high. if the ad5360/ad5361 see a 32-bit data frame, they perform the error check when sync goes high. if the checksum is valid, the data is written to the selected register. if the checksum is invalid, the data is ignored, the packet error check output ( pec ) goes low, and bit 3 of the control register is set. after reading the control register, the error flag is cleared automatically and pec goes high again. 05761-029 update on sync high update after sync high only if error check passed pec goes low if error check fails sclk sdi s ync sclk sdi s ync pec msb d23 lsb d0 msb d31 lsb d8 24-bit data 24-bit data 8-bit checksum d7 d0 24-bit data transfer?no error checking 24-bit data transfer with error checking figure 24. spi write with and without error checking
ad5360/ad5361 rev. a | page 23 of 28 channel addressing and special modes if the mode bits are not 00, then the data word d15 to d0 (ad5360) or d13 to d0 (ad5361) is written to the device. address bit a4 to address bit a0 determine which channel or channels is/are written to, while the mode bits determine to which register (x1a, x1b, c, or m) the data is written, as shown in table 10 and table 11 . data is to be written to the x1a when the a /b bit in the control register is 0 or to the x1b register when the bit is 1. the ad5360/ad5361 have very flexible addressing that allows writing of data to a single channel, all channels in a group, the same channel in group 0 and group 1 or all channels in the device. table 13 shows all these address modes. it shows which group(s) and which channel(s) is/are addressed for every combination of address bit a4 to address bit a0. table 12. mode bits m1 m0 action 1 1 write dac data (x) register 1 0 write dac offset (c) register 0 1 write dac gain (m) register 0 0 special function, used in combination with other bits of a word table 13. group and channel addressing address bit a2 to address bit a0 address bit a4 to address bit a3 00 01 10 11 000 all groups, all channels group 0, ch annel 0 group 1, channel 0 unused 001 group 0, all channels group 0, ch annel 1 group 1, channel 1 unused 010 group 1, all channels group 0, ch annel 2 group 1, channel 2 unused 011 unused group 0, channel 3 group 1, channel 3 unused 100 unused group 0, channel 4 group 1, channel 4 unused 101 unused group 0, channel 5 group 1, channel 5 unused 110 unused group 0, channel 6 group 1, channel 6 unused 111 unused group 0, channel 7 group 1, channel 7 unused
ad5360/ad5361 rev. a | page 24 of 28 special function mode if the mode bits are 00, then the special function mode is selected, as shown in table 14 . bits i21 to i16 of the serial data word select the special function, while the remaining bits are data required for execution of the special function, for example the channel address for data readback. the codes for the special functions in table 16 show the addresses for data readback. table 14. special function mode i23 i22 i21 i20 i19 i18 i17 i16 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 0 0 s5 s4 s3 s2 s1 s0 f15 f14 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 table 15. special function codes special function code data (f15 to f0) action s5 s4 s3 s2 s1 s0 0 0 0 0 0 0 0000 0000 0000 0000 nop. 0 0 0 0 0 1 xxxx xxxx xxxx x [f2:f0] write control register. f4 = 1: temperature over 130c. f4 = 0: temperature under 130c. read-only bit. this bit should be 0 when writing to the control register. f3 = 1: pec error. f3 = 0: no pec error. reserved. read-only bit. this bit should be 0 when writing to the control register. f2 = 1: select register x1b for input. f2 = 0: select register x1a for input. f1 = 1: enable temperature shutdown. f1 = 0: disable temperature shutdown. f0 = 1: soft power-down. f0 = 0: soft power-up. 0 0 0 0 1 0 xx [f13:f0] write data in f13 to f0 to ofs0 register. 0 0 0 0 1 1 xx [f13:f0] write data in f13 to f0 to ofs1 register. 0 0 0 1 0 0 reserved 0 0 0 1 0 1 see table 16 select register for readback. 0 0 0 1 1 0 xxxx xxxx [f7:f0] write data in f7 to f0 to a /b select register 0. 0 0 0 1 1 1 xxxx xxxx [f7:f0] write data in f7 to f0 to a /b select register 1. 0 0 1 0 0 0 reserved 0 0 1 0 0 1 reserved 0 0 1 0 1 0 reserved 0 0 1 0 1 1 xxxx xxxx [f7:f0] block write a /b select registers. f7 to f0 = 0: write all 0s (all channels use x2a register). f7 to f0 = 1: write all 1s (all channels use x2b register). 0 0 1 1 0 0 xxxx xxxx xx [f5:f0] f5 = 1: monitor enable. f5 = 0: monitor disable. f4 = 1: monitor input pin selected by f0. f4 = 0: monitor dac channel selected by f3:f0 (0000 = dac0; 1111 = dac15). f3 = not used if f4 = 1. f2 = not used if f4 = 1. f1 = not used. f0 = 0: mon_in0 selected for monitoring (if f4 and f5 = 1). f0 = 1: mon_in1 selected for monitoring (if f4 and f5 = 1). 0 0 1 1 0 1 xxxx xxxx xxxx xx [f1:f0] gpio configure and write. f1 = 1: gpio is an outp ut. data to output is written to f0. f1 = 0: gpio is an input. data can be read from f0 on readback.
ad5360/ad5361 rev. a | page 25 of 28 table 16. address codes for data readback 1 f15 f14 f13 f12 f11 f10 f9 f8 f7 register read 0 0 0 bit f12 to bit f7 select channel to be read back, channel 0 = 001000 to channel 15 = 010111 x1a register 0 0 1 x1b register 0 1 0 c register 0 1 1 m register 1 0 0 0 0 0 0 0 1 control register 1 0 0 0 0 0 0 1 0 ofs0 data register 1 0 0 0 0 0 0 1 1 ofs1 data register 1 0 0 0 0 0 1 0 0 reserved 1 0 0 0 0 0 1 1 0 a /b select register 0 1 0 0 0 0 0 1 1 1 a /b select register 1 1 0 0 0 0 1 0 0 0 reserved 1 0 0 0 0 1 0 0 1 reserved 1 0 0 0 0 1 0 1 0 reserved 1 0 0 0 0 1 0 1 1 gpio read (data in f0) 2 1 f6 to f0 are dont cares for the data readback function. 2 f6 to f0 should be 0 for gpio read. table 17. dacs selected by a /b select registers a /b select register bits 1 f7 f6 f5 f4 f3 f2 f1 f0 0 dac7 dac6 dac5 dac4 dac3 dac2 dac1 dac0 1 dac15 dac14 dac13 dac12 dac11 dac10 dac9 dac8 1 if the bit is 0, register x2a is selected. if the bit is 1, register x2b is selected. power supply decoupling in any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5360/ad5361 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5360/ad5361 are in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. for supplies with multiple pins (v ss , v dd , dv cc ), it is recommended to tie these pins together and to decouple each supply once. the ad5360/ad5361 should have ample supply decoupling of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capaci- tor should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. digital lines running under the device should be avoided because these couple noise onto the device. the analog ground plane should be allowed to run under the ad5360/ad5361 to avoid noise coupling. the power supply lines of the ad5360/ ad5361 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. it is essential to minimize noise on all vrefx lines. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but this is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground plane, while signal traces are placed on the solder side. as is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. power supply sequencing when the supplies are connected to the ad5360/ad5361, it is important that the agnd and dgnd pins be connected to the relevant ground plane before the positive or negative supplies are applied. in most applications, this is not an issue because the ground pins for the power supplies are connected to the ground pins of the ad5360/ad5361 via ground planes. where the ad5360/ad5361 are used in a hot-swap card, care should be taken to ensure that the ground pins are connected to the supply grounds before the positive or negative supplies are connected. this is required to prevent currents from flowing in directions other than toward an analog or digital ground.
ad5360/ad5361 rev. a | page 26 of 28 interfacing examples the spi interface of the ad5360 and ad5361 is designed to allow the parts to be easily connected to industry standard dsps and microcontrollers. figure 25 shows how the ad5360/ad5361 can be connected to the analog devices, inc., blackfin? dsp. the blackfin has an integrated spi port that can be connected directly to the spi pins of the ad5360 or ad5361, and programmable i/o pins that can be used to set or read the state of the digital input or output pins associated with the interface. spiselx adsp-bf531 ad5360/ ad5361 sck mosi miso pf10 pf8 pf9 pf7 sync sclk sdi sdo reset clr ldac busy 05761-024 figure 25. interfacing to a blackfin dsp the analog devices adsp-21065l is a floating-point dsp with two serial ports (sports). figure 26 shows how one sport can be used to control the ad5360 or ad5361. in this example, the transmit frame synchronization (tfs) pin is connected to the receive frame synchronization (rfs) pin. similarly, the transmit and receive clocks (tclk and rclk) are also connected together. the user can write to the ad5360 or ad5361 by writing to the transmit register. a read operation can be accomplished by first writing to the ad5360/ad5361 to tell the part that a read operation is required. a second write operation with a nop instruction causes the data to be read from the ad5360/ad5361. the dsps receive interrupt can be used to indicate when the read operation is complete. sync sclk sdi sdo reset clr ldac busy ad5360/ ad5361 adsp-21065l tfsx rfsx tclkx rclkx dtxa drxa flag 0 flag 1 flag 2 flag 3 0 5761-025 figure 26. interfacing to an adsp-21065l dsp
ad5360/ad5361 rev. a | page 27 of 28 outline dimensions compliant to jedec standards ms-026-bcc top view (pins down) 40 52 1 14 13 26 27 39 0.65 bsc lead pitch 0.38 0.32 0.22 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.10 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 12.20 12.00 sq 11.80 10.20 10.00 sq 9.80 051706-a figure 27. 52-lead low profile quad flat package [lqfp] (st-52) dimensions shown in millimeters compliant to jedec standards mo-220-vlld-2 112805-0 pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 6.25 6.10 sq 5.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0 .85 0 .80 6.50 ref seating plane 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 0.05 max 0.02 nom 0.25 min exposed pad (bottom view) figure 28. 56-lead lead frame chip scale package [l f csp_vq] 8 mm 8 mm, very thin quad (cp-56-1) dimensions shown in millimeter ordering guide model temperature range packag e description package option ad5360bstz 1 ?40c to +85c 52-lead low profile quad flat pack [lqfp] st-52 ad5360bstz-reel 1 ?40c to +85c 52-lead low profile quad flat pack [lqfp] st-52 ad5360bcpz 1 ?40c to +85c 56-lead lead frame chip scale package [l f csp _vq] cp-56-1 ad5360bcpz- reel7 1 ?40c to +85c 56-lead lead frame chip scale package [l f csp _vq] cp-56-1 ad5361bstz 1 ?40c to +85c 52-lead low profile quad flat pack [lqfp] st-52 ad5361bstz-reel 1 ?40c to +85c 52-lead low profile quad flat pack [lqfp] st-52 ad5361bcpz 1 ?40c to +85c 56-lead lead frame chip scale package [l f csp _vq] cp-56-1 ad5361bcpz- reel7 1 ?40c to +85c 56-lead lead frame chip scale package [l f csp _vq] cp-56-1 eval -ad5360ebz 1 evaluation board eval-ad5361ebz 1 evaluation board 1 z = rohs compliant part.
ad5360/ad5361 rev. a | page 28 of 28 notes ?2007C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05761-0-2/08(a)

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